1. Field of the Invention
The present invention relates to a semiconductor device and to a manufacturing process thereof and, more particularly, to a semiconductor device in which a silicon oxide film formed on an uneven pattern is planarized and to a manufacturing process thereof including a step of planarizing the silicon oxide film.
2. Description of the Related Art
At present, various types of semiconductor devices such as microcomputers, memories, and gate arrays are incorporated in many kinds of electric appliances including personal computers, work stations, etc. In these semiconductor devices, a plurality of elements such as transistors are integrated in a semiconductor substrate, and signal wires connecting these elements are almost necessarily multilayered. Accordingly, there is insulation between an element formed on the semiconductor substrate and a signal wire formed in an upper layer of the device consisting of an insulating layer formed on the element. There is also insulation between the signal wire and another signal wire formed on a further upper layer consisting of an insulating layer formed on the signal wire of the lower layer. Most of the insulating layers under the signal wires of both upper and lower layers are made of silicon oxide films, and planarity of the films is an essential requirement. This is because the formation of signal wires requires a series of photolithographic processes which includes forming a signal wire material on the surface of a silicon oxide film serving as an insulating layer, applying a resist thereon, irradiating the resist with light using a mask, etching the irradiated resist to leave resist only in the signal wire pattern, and further etching the signal wire material using the etched resist as a mask. Accordingly, there is a disadvantage in that a step difference in an insulating layer under a signal wire causes the signal wire formed on the insulating layer and further the resist formed thereon to create similar step differences. Therefore, projected light gets out of focus and the resist is not etched in the desired pattern, which may cause a short circuit between adjacent signal wires or an open in a signal wire.
For example, FIG. 16 shows a conventional semiconductor device, disclosed in the Japanese Laid-Open Patent Publication (unexamined) Hei 4-213829, which includes a semiconductor wafer 1 having grooves 2 in a main surface of the semiconductor wafer 1, wires 3 formed on the main surface, an oxide layer 4 formed on the semiconductor wafer 1 in the grooves 2 and over the wires 3 employing tetraethylorthosilicate (TEOS) and ozone (O.sub.3) under a prescribed pressure, and an oxide layer 5 formed on the oxide layer 4 employing TEOS and ozone under a pressure lower than the prescribed pressure applied during forming the oxide layer 4.
Another Japanese Laid-Open Patent Publication (unexamined) Sho 59-98726 discloses that a silicon oxide film is formed employing silane (SiH.sub.4), SiHCl.sub.3 and hydrogen peroxide (H.sub.2 O.sub.2), and another Japanese Laid-Open Patent Publication (unexamined) Hei 6-349747 discloses that when forming a silicon oxide film employing TEOS and hydrogen peroxide, desirable step coverage is achieved. Further, Japanese Laid-Open Patent Publication (unexamined) Hei 5-182918 discloses that when forming a silicon oxide film employing tetraethoxysilane (Si(OC.sub.2 H.sub.5).sub.4) as an organic silane and hydrogen peroxide, a step coverage superior to that of employing ozone instead of hydrogen peroxide is achieved.
A silicon oxide layer formed by CVD (Chemical Vapor Deposition) employing a silicon compound such as silane and hydrogen peroxide can fill an extremely fine gap between two wires (0.25 .mu.m or less, for example), and shows a superior fluidity and a self-planarizing character. Therefore CVD has come to attract a great deal of attention as a next-generation method of forming planarized insulating layers in place of the conventional SOG (Spin On Glass) method or the like. This was reported in "NOVEL SELF-PLANARIZING CVD OXIDE FOR INTERLAYER DIELECTRIC APPLICATION" (Technical Digest of IEDM 1994) and also in "PLANARIZATION FOR SUB-MICRON DEVICES UTILIZING A NEW CHEMISTRY" (Proceedings of DUMIC Conference 1995).
In the conventional semiconductor device as shown in FIG. 16, an oxide layer is formed employing TEOS and ozone, as mentioned above, and therefore a problem exists in that irregularity in coverage of the oxide layers 4 and 5 in the vicinity of the wires 3 is excessively large. In other words, the step coverage for oxide layers 4 and 5 is inadequate. Another problem exists in that when oxide layers 4 and 5 of almost equal thickness are respectively formed on the semiconductor wafer 1 and the wires 3 and, as a result, the step difference 7 on the upper face of the oxide layer 5 is as much as the height of the wires 3.
FIG. 17 shows an experimental result of forming an oxide layer employing silane and hydrogen peroxide instead of TEOS and ozone to overcome the mentioned problems. In FIG. 17, a semiconductor device includes a semiconductor substrate 11, aluminum wires 12 and silicon oxide film 13 formed on the semiconductor substrate 11, and an oxide layer 14 formed on the silicon oxide film 13 by CVD employing silane and hydrogen peroxide. It was acknowledged that the concave depth is large (so that the occurrence of inadequate planarization is greater) at the peripheral part as compared with the internal part of the wire formation region 15 where the aluminum wires 12 are formed.
The following is an explanation for the inadequate planarization. Silanol (Si(OH).sub.4) of low viscosity and superior fluidity is produced from silane and hydrogen peroxide by the following chemical reactions: ##STR1##
Silanol undergoes a reaction of dehydrating polymerization due to hydrolysis or thermal energy, and a silicon oxide film (SiO.sub.2) is produced in the following manner: EQU nSi(OH).sub.4 .fwdarw.nSiO.sub.2 +2nH.sub.2 O (2)
The silicon oxide produced with silanol of high fluidity in this manner fills an extremely fine gap between the wires (i.e., sufficient step coverage is achieved), resulting in superior self-planarizing characteristics. However, fluidity of the silanol occurring at the end portion of the region 15 is deficient, producing inadequate gap filling between the wires 12 eventually resulting in inadequate planarization.